This disclosure relates generally to the field of complementary metal-oxide-semiconductor (CMOS) device fabrication, and more particularly to formation of a stressed liner over a silicided CMOS device.
Stressed liners, which may include a nitride film deposited over a device, are used to boost performance for CMOS devices such as field effect transistors (FETs). A stressed liner with compressive stress enhances hole mobility in a channel of a p-type FET (PFET), and a stressed liner with a tensile stress enhances electron mobility in a channel of an n-type FET (NFET). The stressed liner may be deposited over the device after contact formation. For devices in which the contacts are silicide, the stressed liner is deposited on the silicide contact regions after formation of the silicide in the contact regions. The stressed liner covers the silicide contacts, usually making direct contact with the silicide contacts.
In order to reach relatively high stress values in a stressed liner so as to increase device performance, a nitride stressed liner is deposited over the FET device at a relatively high temperature (for example, in a range from about 400° C. to about 500° C.). Stressed liner deposition may take several minutes, during which time the FET device is exposed to the relatively high temperature. Further, the stress experienced by the device from the stressed liner may be relatively high. To enhance carrier mobility in a FET channel, a stressed liner having a compressive stress of about 3.5 gigapascals (GPa) may be deposited over a PFET device, or a stressed liner having a tensile stress of about 1 GPa may be deposited over an NFET device. The combination of the relatively high stress and high temperature processing may cause silicide degradation in silicide contact regions in the device, particularly in PFET silicide contacts that are formed in a silicon germanium (SiGe) substrate. The degraded silicide may appear spotty or have voids that can cause contact opens and circuit fails, which reduce device yield for the CMOS fabrication process. Reducing the liner deposition temperature and liner stress may mitigate silicide degradation; however, reduction of liner deposition temperature and liner stress results in a lower-performance FET device.